Logic devices such as FPGAs are used to implement large systems that include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, routing, delay annotation, and timing analysis.
Delay annotation may involve performing logic cell delay annotation where delays related to a logic cell are computed based on the configuration and settings of the cell. Delay annotation may also involve performing routing delay annotation where delays related to a routing connection are computed based on the structure and configuration of the routing connection with respect to other routing connections on a netlist. Routing delay annotation often involves running a modeling program in order to simulate the system design.
When changes are made to a system design, the system design is often re-annotated in its entirety. When only incremental changes are made to a system design, having to re-annotate an entire system design may require a significant amount of additional time that impacts the overall compile time of a system design.
Thus, what is needed is an efficient and effective method and apparatus for performing incremental delay annotation.